In semiconductor electronics, it is known to adjust operating parameters of digital circuits, e.g. based on static logic, in such a way that the circuit operates with an operating frequency which is as high as possible and with a supply voltage which is as low as possible. However, due to process variations in manufacturing the integrated semiconductor circuit and due to performance degradations, e.g. induced by aging, it is typically necessary to introduce timing margins, which ensure that the circuit is operable even under a worst case scenario, e.g. in the case of strong performance degradations due to aging and process variations.
Accordingly, there is a need for efficient methods and devices, which allow for evaluating timing margins in an integrated circuit.